A 0.4 V 63 mu W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator

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초록

This paper presents a delta-sigma modulator operating at a supply voltage of 0.4 V. The designed delta-sigma modulator uses a proposed hybrid switching integrator and operates at a low supply voltage without clock boosting or bootstrapped switches. The proposed integrator consists of both switched-resistor and switched-capacitor operations and significantly reduces distortion at a low supply voltage. Variation in the turn-on resistance, which is the main source of distortion, is avoided by placing the switches at the virtual ground node of the amplifier. The proposed low-voltage design scheme can replace commonly-used clock boosting techniques, which rely on internal high-voltage generation circuits. A fabricated modulator achieves a 76.1 dB signal-to-noise-plus-distortion ratio (SNDR) and an 82 dB dynamic range at a 20 kHz bandwidth. The measured total power consumption is 63 mu W from a 0.4 V supply voltage. The measured results show robust SNDR performance, even at +/- 10% supply voltage variations. The measured results also show stable performance over a wide temperature range.

키워드

Hybrid switching integrator; low-power deltasigma modulator; THRESHOLD-VOLTAGE INSTABILITY; MOSFETS; 0.5-V; ADC
제목
A 0.4 V 63 mu W 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator
저자
Yoon, Younghyun; Choi, Danbi; Roh, Jeongjin
DOI
10.1109/JSSC.2015.2468857
발행일
2015-10
유형
Article; Proceedings Paper
저널명
IEEE Journal of Solid-State Circuits
권
50
호
10
페이지
2342 ~ 2352