Built-In Phase Noise Measurement System for Multi-GHz Phase-Locked Loops

초록

This article introduces a fully integrated on-chip phase noise measurement (PNM) system for multi-GHz phase-locked loops (PLLs). Typically, PLL performance is commonly assessed using high-precision external measurement equipment; although accurate, such equipment is costly and unsuitable for efficient parallel testing. Built-in self-test (BIST) approaches provide a compelling alternative; however, existing solutions exhibit a tradeoff between measurement accuracy and test efficiency. While maintaining the key benefits associated with BIST-based evaluation, this study aims to bridge the gap between conventional measurement approaches and built-in PNM. Within a single-chip architecture, the PLL and the built-in PNM are unified in the proposed design to achieve this objective. By leveraging the flexibility of an all-digital PLL (ADPLL), the proposed PNM can effectively track phase noise across diverse PLL output characteristics. Across multiple fabricated chips and a range of PLL configurations, the proposed system maintains measurement error within 5% while supporting offset frequencies up to 25 MHz and delivering subpicosecond jitter resolution within the 1-MHz range.

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