A Charge-Domain ELDC Technique with CDAC-Reusing for High-Speed Delta-Sigma Modulators

초록

This paper proposes a compact charge-domain excess loop delay compensation (ELDC) technique that reuses the capacitive digital-to-analog converter (CDAC) of a 4-bit asynchronous successive approximation register (ASAR) quantizer for high-speed continuous-time delta-sigma modulators (CTDSMs). By eliminating the auxiliary CDAC traditionally required for charge-domain ELDC, the proposed approach simplifies the overall architecture and reduces the total CDAC capacitance by nearly 50 %, enabling a more compact and integration-friendly design. The 4-bit ASAR employs a monotonic switching scheme to minimize switching activity. To enhance noise shaping under a low oversampling ratio (OSR) without adding extra integrators, a second-order analog noise-coupling filter (ANCF) is also incorporated. The proposed technique is validated through its implementation in a high-speed CTDSM fabricated in a 28 nm CMOS process. The prototype occupies an area of 0.045 mm2 and consumes 4.74 mW from a 1 V supply while operating at a 500 MHz sampling rate. It achieves a signal-to-noise-and-distortion ratio (SNDR) of 73.5 dB and a dynamic range (DR) of 76.3 dB over a 12.5 MHz bandwidth, corresponding to a Schreier figure-of-merit (FoM) of 170.5 dB based on DR. © 2013 IEEE.

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