A 103 dB DR Fourth-Order Delta-Sigma Modulator for Sensor Applications

초록

This paper describes a fourth-order cascade-of-integrators with feedforward (CIFF) single-bit discrete-time (DT) switched-capacitor (SC) delta-sigma modulator (DSM) for high-resolution applications. This DSM is suitable for high-resolution applications at low frequency using a high-order modulator structure. The proposed operational transconductance amplifier (OTA), used a feedforward amplifier scheme that provided a high-power efficiency, a wider bandwidth, and a higher DC gain compared to recent designs. A chopper-stabilization technique was applied to the first integrator to remove the 1/f noise from the transistor, which is inversely proportional to the frequency. The designed DSM was implemented using 0.35 mu m complementary metal oxide semiconductor (CMOS) technology. The oversampling ratio (OSR) was 128, and the sampling frequency was 128 kHz. At a 500 Hz bandwidth, the signal-to-noise ratio (SNR) was 100.3 dB, the signal-to-noise distortion ratio (SNDR) was 98.5 dB, and the dynamic range (DR) was 103 dB. The measured total power dissipation was 99 mu W from a 3.3 V supply voltage.

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