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A 6-bit Digitally Controlled Vector-Sum Phase Shifter with Current Steering Architecture
- 이정수;
- 장웅주;
- 장광호;
- 장태환
초록
This paper presents a 6-bit Ku-band vector-sum phase shifter (VSPS) designed for beamforming applications operating in the 10.7–12.7 GHz range. A two-stage RC polyphase filter is adopted for quadrature signal generation, achieving a maximum gain imbalance of 0.218 dB and a maximum phase error of 1.636°, outperforming RL-based alternatives in integration and broadband accuracy. The core uses a digitally controlled current-steering architecture with MOSFET-based RF cells that synthesize precise phase states via binary-weighted vector summation. This structure enables 5.625° resolution, compact layout, and low power operation. Post-layout electromagnetic(EM) simulations show RMS phase errors under 2.5°, gain errors between 0.3 to 0.5 dB, and average gain from -4.55 to -2.17 dB. With only 15.8 mW DC power consumption, the design is efficient and scalable. The proposed architecture combines high resolution, low power, and robust performance, making it well-suited for next-generation phased-array systems in Ku-band satellite communications.
키워드
- 제목
- A 6-bit Digitally Controlled Vector-Sum Phase Shifter with Current Steering Architecture
- 저자
- 이정수; 장웅주; 장광호; 장태환
- 발행일
- 2026-01
- 유형
- Y
- 저널명
- IDEC Journal of Integrated Circuits and Systems
- 권
- 12
- 호
- 1
- 페이지
- 43 ~ 48