Efficient machine-learning-based built-in self-calibration scheme for SAR-ADCs

초록

Imperfect fabrication induces capacitor-mismatches that significantly affect the linearity of the successive-approximation-register (SAR) analog-to-digital converter (ADC), leading to significant yield loss. A number of attempts to calibrate the linearity of the SAR ADCs are suffering from the following remarkable limitations: (1) the search resolution for the calibration process restrained by practical (or limited) calibration process time, and (2) the training set with low correlation to the validation set for the machine-learning-driven calibration approaches. To overcome those issues, this paper proposes a machine-learning-based built-in self-calibration scheme for split-SAR ADCs in a system-on-a-chip (SoC). For the configuration, the split-SAR ADC in a SoC is connected with an external digital-to-analog converter (DAC) on the load board for calibration purpose. Two parallel sub-ADCs in the ADC include their capacitive DACs whose binary-weighted capacitor-arrays consist of variable capacitors. The optimal signatures for this work are devised by differently exploiting our previous work, where the previous work calibrates the split-SAR ADC by effectively comparing the binary-weighted capacitors in the ADC. Based on this, this work is performed in the two steps. Firstly, the training process is conducted by generating the efficient two signatures and the two reference values. The first signature is the input control voltages (called input signature) for the variable capacitors of the training set, which are determined by the process restrained by practically limited process time. The second signature is the harmonics (called output signature) of the training set (with the input control voltages obtained above set) by using a DAC on the load board and on-chip digital-signal-processor (DSP) core available in an SoC. The reference values are another set of the input/output signatures which is even more accurately measured during sufficiently long time. Then, the MARS generates the strongly correlated mapping functions among the input/output signatures and their reference values using an on-chip DSP core. Secondly, for the validation process, the input/output signatures are measured from the validation set as in the training process. Those signatures are then applied to the obtained mapping functions to predict the accurate input control voltages for the variable capacitors. Therefore, the ADC linearity can be significantly enhanced based on the proposed self-calibration. The simulation results verified that the total-harmonic-distortion and the signal-to-noise-and-distortion ratio were enhanced from 44-dB to 49-dB and from 43-dB to 48-dB, respectively. Copyright © 2026 The Institute of Electronics, Information and Communication Engineers This work is licensed under a Creative Commons Attribution NonCommercial, No Derivatives 4.0 License.

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