A Timing Relaxed Pre-Decision Feedforward Equalizer for DSP-Based Wireline Receiver Using Hardware-in-the-Loop Verification on FPGA

초록

This paper presents a critical-timing-relaxed pre-decision feedforward equalizer (pDFFE) designed for high-speed digital signal processor (DSP)-based wireline receivers. Since conventional decision feedback equalizer (DFE) suffers from an increasing timing burden due to recursive feedback loops, which hinder parallelization and scalability, the proposed pDFFE architecture eliminates the feedback path by replacing post-cursor inter-symbol interference (ISI) cancellation with feed-forward equalizer (FFE)-based decisions. The overall system employs a hardware-in-the-loop (HIL) verification platform based on the Versal ACAP, integrating a DSP engine with sign-sign LMS (SS-LMS) adaptation. The power and area of the proposed DSP in 28nm CMOS layout are estimated to be 176.5mW and 0.201mm(2), respectively. Both simulation and measurement results under -24dB channel loss at Nyquist frequency demonstrate reliable BER performance comparable to the conventional DFE, while achieving single-clock latency and improving area efficiency, from a minimum of 10 % to a maximum of 47 %, compared to conventional architectures.

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