시그마-델타 A/D 컨버터용 디지털 데시메이션 필터 설계

초록

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in 0.25-㎛ CMOS technology and incorporates 1.36 ㎟ of active area, shows 4.4 ㎽ power consumption at clock rate of 2.8224 ㎒. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

키워드