Split-Capacitive SAR-ADC based on Efficient Code-Width Calibration

초록

Successive-approximation-resistor (SAR) analog-to-digital converter (ADC) suffers from the linearity degraded by mismatch in the bridge capacitor and parasitic capacitances from the least-significant-bit (LSB) capacitor array. This paper proposes a foreground calibration design scheme to apply a perfectly linear ramp signal to an ADC under calibration, and to quantify the errors in the wide code width using the proposed width detection block in the postprocessing manner. To validate the performance of this work, the simulation was performed with a 12-bit split-capacitive SAR ADC, and the DNL and the INL results were reduced (enhanced) by 6.03LSB and 3.01LSB, respectively.