Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC

초록

This article presents a design methodology for com-pact single-channel 1 GS/s 8-bit 3-stage capacitor-array-assistedcharge-injection DAC-based SAR ADC. A detailed frameworkof an information rate density (IRD) is mainly investigated inthis work. With the proposed framework, an 8-bit prototypeADC reaches the highest IRD thanks to the optimum choiceof DAC construction. To improve the performance of the ADC,we propose various circuit techniques such as 1) DC dependencecompensation of charge-injection cell (ci-cell), 2) up-then-downDAC switching sequence, and 3) metastability detection to pre-vent the sparkle code error. The prototype ADC was fabricatedin a 28-nm CMOS process and occupies an ultra-compactactive area of 0.000261 mm(2), the smallest among the previouslyreported designs. At a 1.0 V supply voltage and 1 GS/s operation,the proposed ADC achieves an SNDR of 43.5 dB and dissipates2.61 mW at the Nyquist rate, resulting in the state-of-the-art IRDof 470 TS/s<middle dot>conv/mm(2)

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