Pixelated source polarization optimization for hyper-NA EUV lithography

초록

As extreme ultraviolet (EUV) lithography advances into the hyper-numerical aperture (hyper-NA, NA > 0.75) regime, achieving sub-8 nm resolution while maintaining a sufficient process window (PW) becomes increasingly critical for enabling next-generation semiconductor nodes. According to the latest scaling roadmaps, metal pitches are expected to shrink below 16 nm, driving the need for advanced lithographic techniques that overcome the limitations of conventional polarized illumination methods. Although transverse electric (TE) and transverse magnetic (TM) polarization approaches have shown effectiveness in high-NA systems down to 15 nm pitch, their impact saturates as vectorial light–matter interactions become more dominant. To address these challenges, we present a pixelated source polarization optimization (SPO) technique tailored for hyper-NA EUV lithography. This method enables spatially resolved polarization control at each pixel within the source pupil, expanding the degrees of freedom beyond conventional uniform-polarization schemes. Rigorous electromagnetic simulations using the Fastlitho platform demonstrate that pixelated SPO extends resolution capabilities beyond previous limits, achieving 11 nm pitch for line-space (L/S) and 15 nm pitch for contact-hole (C/H) patterns—while maintaining peak normalized image log-slope (NILS) > 2.0 and robust normalized depth of focus (nDOF) across X and Y directions. Beyond resolution improvement, pixelated SPO simultaneously enhances NILS and DOF, thereby expanding process margins and ensuring patterning feasibility for complex DRAM and logic layouts. Previous results also confirm consistent CD control and lithographic success for mixed-pattern DRAM configurations incorporating L/S, diagonal, and C/H arrays. This study establishes pixelated SPO not only as an enhancement technique, but as a foundational enabler for future hyper-NA nodes, potentially supporting beyond-A2 scaling as projected in the ASML/imec roadmap. By pushing resolution boundaries while preserving process stability and pattern fidelity, pixelated SPO opens a new design space for advanced memory and logic device generations.

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