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A Power Supply Rejection Compensated External Capacitor-Less Low Drop-Out Regulator
- Guo, Tian;
- Moon, Jiho;
- Roh, Jeongjin
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0초록
This paper presents a compensation technique for a power supply rejection (PSR) improved external capacitor-less low drop-out (LDO) regulator. A replica circuit is used to cancel the power supply noise generated by the gate-source parasitic capacitor of the pass transistor. This design was fabricated in a 0.18 μm bipolar-CMOS-DMOS (BCD) technology with a power supply of 1.8 V. The active core chip area is 0.023 mm2, and the entire proposed LDO consumes 65 μA of quiescent current. It has a drop-out voltage of 200 mV, and the maximum load current is 60 mA. The measured PSR has a maximum-22 dB enhancement compared with a conventional uncompensated LDO when delivering a current of 60 mA. © 2019 IEEE.
키워드
external capacitor-less LDO; power management integrated circuit (PMIC); PSR compensated LDO; Electric current regulators; Programmable logic controllers; Capacitor-less; Compensation techniques; Low dropout regulator; Low-dropout regulators; Parasitic capacitors; Power management integrated circuits; Power supply rejection; PSR compensated LDO; Drops
- 제목
- A Power Supply Rejection Compensated External Capacitor-Less Low Drop-Out Regulator
- 저자
- Guo, Tian; Moon, Jiho; Roh, Jeongjin
- 발행일
- 2019-10
- 유형
- Conference Paper
- 저널명
- Proceedings - 2019 International SoC Design Conference, ISOCC 2019
- 페이지
- 54 ~ 55
- 언어
- ENG
- 출판사
- Institute of Electrical and Electronics Engineers Inc.
- 발행국가
- 미국
- 분량
- 2 페이지
- ISSN
- P 2163-9612