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High speed recursion-free CORDIC architecture
- Abdulla, Shakeel S.;
- Nam, Haewoon;
- Swartzlander, Jr. Earl E.;
- Abraham, Jacob A.
Citations
SCOPUS
0초록
This paper proposes a novel unrolled CORDIC (Co-Ordinate Rotation DIgital Computer) architecture based on parallel operations of a series of micro-rotation stages in the conventional CORDIC. To improve the speed and lower the energy consumption, a Wallace tree reduction is used for the summation of the computed parallel terms. For a large number of micro-rotation stages, a first order approximation is used to reduce the complexity while maintaining the output data accuracy. The circuit has been implemented using a 65nm process. The results show a speed improvement of 20% and an energy-delay reduction of 27% with a minimal expense of 5% increase in the circuit area relative to a conventional CORDIC architecture. © 2010 IEEE.
키워드
Digital computers; Energy-delay; Co-ordinate rotation digital computers; Wallace tree; Rotation; Speed improvement; Output data; Parallel operations; Microrotation; Energy utilization; Computer architecture; First-order approximations; Co-ordinate rotation digital computers; Energy-delay; First-order approximations; Microrotation; Output data; Parallel operations; Speed improvement; Wallace tree; Digital computers; Energy utilization; Rotation; Computer architecture
- 제목
- High speed recursion-free CORDIC architecture
- 저자
- Abdulla, Shakeel S.; Nam, Haewoon; Swartzlander, Jr. Earl E.; Abraham, Jacob A.
- 발행일
- 2010-09
- 유형
- Conference Paper
- 저널명
- International System on Chip Conference
- 페이지
- 65 ~ 70
- 언어
- ENG
- 분량
- 6 페이지
- ISSN
- E 2164-1706
P 2164-1676