센서용 Incremental 델타-시그마 아날로그 디지털 변환기 설계

초록

This paper presents the design of the incremental delta-sigma ADC. The proposed circuit consists of pre-amplifier, S &H circuit, MUX, delta-sigma modulator, and decimation filter. Third-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a 0.18 ㎛ CMOS technology. The designed circuit show that the modulator achieves 87.8㏈ signal-to-noise and distortion ratio (SNDR) over a 5 ㎑ signal bandwidth and differential nonlinearity (DNL) of ± 0.25LSB, integral nonlinearity (INL) of ± 0.2 LSB. Power consumption of delta-sigma modulator is 941.6 ㎼. It was decided that N cycles are 200 clock for 16-bits output.

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