High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications

초록

In this paper, we propose a high-precision built-in phase noise measurement (PNM) circuit based on a ΔΣ time-to-digital converter (TDC) and a pseudo-delay-locked loop (DLL). The designed ΔΣ TDC uses a hybrid continuous-time (CT) discrete-time (DT) loop filter. The first integrator consists of a phase frequency detector (PFD), a charge pump (CP), and an operational transconductance amplifier (OTA)-based integrator operating as a CT filter. The OTA-based integrator ensures a constant output current, improving linearity. Other loop filters employ a switched capacitor integrator as a DT filter. The proposed architecture processes time-domain signals and has the advantage of containing both CT and DT loop filters. This architecture is less sensitive to to CT ΔΣ. Pseudo-DLL provides a precise reference delay. The proposed PNM circuit is fabricated in the 28 nm CMOS process, occupies an area of 0.113 mm, and consumes 11.61 mW with a 1 V power supply while running at a clock rate of 250 MHz. The rms jitter from 100 kHz to 2 MHz measured by an external instrument and PNM are 1.77 and 1.8137 ps, respectively, while the corresponding error is less than 3%. The proposed PNM circuit can achieve approximately 2 ps from 100 kHz to 4 MHz at the optimum noise transfer function (NTF) zero location. IEEE

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