Advanced Metallizations for Next Generation Semiconductor Packaging Technology

초록

In recent years, many researches have been focused on the miniaturization of the integrated circuit (IC) feature size to improve the performance of semiconductor devices. However, we are facing the problems such as physical limit of the miniaturization and then increasing processing cost. To overcome these problems the Through-Si-Via (TSV) interconnection, a kind of the 3D interconnection, is a promising technology that could achieve high density, lower energy consumption and high performance in the IC. © 2023 Japan Institute of Electronics Packaging.